Electrostatic discharge (ESD) induced damage is a devastating problem to integrated circuit (IC) parts. In order to protect IC parts against ESD failures, on-chip ESD protection circuits (hereinafter “ESD devices” for brevity) are required for virtually all practical IC products. On-chip ESD protection circuit design emerges as a major design challenge as IC technologies migrate into the very-deep-sub-micron (VDSM) regime, particularly for mixed-signal and RF ICs.
ESD events, which are inevitable in IC manufacturing, assembly, and application, generate huge over-current and over-voltage transients that can fatally damage electronic components. ESD failure becomes a major IC reliability problem to the semiconductor industry, and accounts for 30–50% of total field failures. Therefore, on-chip ESD devices are required for all IC chips. In principle, an ESD protection device, which remains in the off state in normal operation, is triggered by an ESD pulse to form a low-impedance discharging path to shunt the current transient safely and to clamp the pad voltage to a sufficiently low level, therefore protecting an IC chip from being ESD-damaged.
While many different kinds of general purpose IC physical design verification methods, such as design rule checking (DRC) and layout versus schematic (LVS) exist, few physical design verification methods and computer-aided-design (CAD) software tools are available for on-chip ESD protection circuit design. Particularly, no physical design verification method and CAD tool are currently available that can perform comprehensive ESD-function-based physical design verification at the design layout level without resorting to device-model-based schematic/simulation level checking.
In on-chip ESD protection circuit design, after layout and before IC fabrication, comprehensive physical layout design verification should be performed to thoroughly verify the layout design. Physical layout design verification helps to avoid fatal layout errors and reduce design time and efforts. Unfortunately, the currently dominating trial-and-error ESD protection approaches do not facilitate any practical ESD device design verification methods and software.
Aside from the challenges associated with the design of circuits for on-chip ESD devices, comprehensive ESD device design verification at the whole chip level becomes critical to the success of complex IC chip design. An automatic ESD device extractor at the layout level can play an important role in IC protection. ESD device extraction should be the first step in any design verification to enable further layout-schematic checking and ESD circuit simulation at the whole chip level.
Compared with the research efforts made in ESD device design, very limited work has been done in realizing ESD device extraction. The current challenges in developing ESD device extraction tools are as follow. First, extraction of ESD device is different from that of extracting normal IC devices in that ESD devices are often unconventional devices in nature. Conventional IC devices, such as MOSFET, can be extracted using basic Boolean operation of layout features as set forth in U. Lauther, “An O(N log N) Algorithm For Boolean Mask Operations”, Proc. 18th DAC, pp 555–562, 1981. However, ESD devices have very complicated structures and irregular layout patterns which cannot be extracted using existing conventional device extractors.
Second, ESD transient current often causes the turn-on of parasitic ESD-like devices (also referred to herein as “ESD devices” for simplicity) such as may exist inside the protected core IC circuit or in the ESD protection network, before the intentional ESD devices can be triggered to perform ESD protection. The chip level. Therefore, there is a need for reliable parasitic ESD device extraction, and analysis according to the ESD stressing conditions.
In T. Li, C. Tsai, E. Rosenbaum and S. M. Kang, “Modeling, Extraction and Simulation of CMOS I/O Circuits under ESD Stress”, Proc. IEEE ISCAS, Vol.6, pp 389–392, 1998., an ESD CAD tool is presented for detecting parasitic BJT (bipolar junction transistors) type ESD devices in MOSFET ESD protection structures under ESD stresses. In Q. Li and S. M. Kang “Technology Independent Arbitrary Device Extractor”, Proc. 10th Great Lakes Symp. VLSI, pp 143–146, 2000., a technique to extract irregular ESD devices is presented. This technique, however, adopts a time-consuming top-down recognition approach, uses a redundancy-prone individual model graph recognition method, and mainly focuses on intentional ESD devices.
T. Li, Y. Hun and S. Kang, “Automated Extraction of Parasitic BJT's for CMOS I/O Circuits under ESD Stress”, IRW Final Report, pp 103–109, 1997., presents an ESD-stress-dependent stress annotation technique to extract parasitic BJT devices. This technique does not have the desired capacity to extract any parasitic ESD devices independent of ESD stressing conditions, which is critical to verify ESD protection design at the full chip level.
An alternative device extraction technique is the procedural decision tree (D-tree) method reported in NCA/DVS Training Guide, NCA Corporation, California, USA. A D-tree is a structured set of sequential decisions used to refine an initial hypothesis formed when a characteristic layout feature to a specific device is found. In device recognition, the program detects a characteristic layout feature and goes through user-defined procedural D-tree routines to recognize a device. While simple to implement, the D-tree approach requires procedural details describing a device to be detected, thus increasing the amount of details that must be reprogrammed for each different IC technology. It also has the disadvantage of requiring a huge amount of intermediate mask/shape data. Hence, D-tree based extraction tools require complex device description, extensive computing time, and a large intermediate database.
Some reported device extractors such as in the aforementioned Li and Kang article, or in A. Brown and P. Thomas, “Goal-Oriented Subgraph Isomorphism Technique For IC Device Recognition” Comms., Speech & Vision, IEE Proc. I, V135 N6, pp 141–150, 1988., use a top-down approach in which a characteristic feature of a device is specified as the root for the device model graph, and the recognition of the device is triggered by the discovery of its root. This approach can be an efficient solution when a limited number of device types are considered. However, its efficiency decreases significantly as the number of model graphs is increased, as in the case of ESD protection circuit design.
However, an ESD device extractor should desirably deal with many device types including the classic ESD device types, e.g., ggNMOS (grounded-gate NMOSFET), gcNMOS (gate-coupled NMOSFET), BJT, diode and SCR, as well as any new ESD devices, e.g., a dual-direction SCR ESD device as presented in A. Wang and C. Tsay, “On a Dual-Polarity On-Chip Electrostatic Discharge Device”, IEEE Tran. Electron Devices, Vol. 48, No. 5, pp 978–984, May 2001.
Aside from the challenges associated with on-chip ESD device extraction, i.e., identification, an automatic ESD device layout extractor would desirably enable further layout-schematic checking and ESD circuit simulation at the whole chip level.
Q. Li, Y. Hun, J. Chen, P. Bendix and S. Kang, “ESD Design Rule Checker”, Proc. IEEE ISCAS, pp 499–502, 2001., discusses an ESD design rule checking program, based upon the ESD device extraction tool proposed in the aforementioned Li and Kang article, that checks intentional ESD devices against given ESD design rules. This application may be limited by the features of the extraction tool of the aforementioned Li and Kang article.
S. Sinha, H. Swaminathan, G. Kadamati and C. Duvvury, “An Automatic Tool for Detecting ESD Design Errors”, Proc. EOS/ESD Symp., pp 208–217, 1998., reported an ESD design error-checking tool that performs simple and traditional metal bus resistance and diffusion spacing checks only.
M. Baird and R. Ida, “VerifyESD: A Tool for Efficient Circuit Level ESD Simulation of Mixed-Signal ICs”, Proc. EOS/ESD, pp 465–469, 2000., presented an ESD device verification tool that is simply a SPICE (Simulation Program with Integrated Circuit Emphasis) pre/post processor capable of analyzing a given circuit netlist. This tool does not address complex ESD device extraction problems.
Further, while there have been proposed device extraction techniques for the identification of some ESD device structures, no tool or system known to the inventors has yet put forth a means for calculating the critical operating parameters of those ESD devices identified and using the critical operating parameters in order that a thorough, automatic, layout level design verification may take place for the whole IC chip to ensure that the IC is adequately protected from ESD events.
Therefore, what is needed in the art for proper IC design verification is reliable, complete, automatic, ESD device extraction and inspection method at the design layout level to ensure full ESD protection of ICs. It is also desirable that such a method should be CAD-based and that it should enable further layout-schematic checking and ESD circuit simulation at the whole chip level. It is also very desirable that the final output of the netlist of such a method should contain all ESD-type devices capable of being turned on under an ESD pulse, whether the devices are intentional ESD devices or parasitic (unintentional) ESD-like devices.